FIG. 7 shows a memory system 101. The memory system 101 has a memory controller device 102 and a memory device 103. The memory controller device 102 has a memory controller 104 and a physical layer part 105 for receiving/transmitting data. The physical layer part 105 is provided with a data reception circuit 113.
A plurality of SDRAM (Synchronous DRAM) (not shown) are mounted in the memory device 103. A clock supply route to the plurality of SDRAMs in the memory device 103 is constructed by a daisy chain. The memory device 103 and the physical layer part 105 are connected to each other through a clock signal line CW. A clock CK is input through the clock signal line CW and the clock supply route to each of the plurality of SDRAMs. Furthermore, a read command output from the memory controller 104 is input to each of the plurality of SDRAMs through a command signal (not shown) and a command supply route (not shown).
The plurality of SDRAMs in the memory device 103 and the data reception circuit 113 are connected to one another through a strobe signal line SW and a data signal line DW. Data signals DQ output from the plurality of SDRAMs are input to the data reception circuit 113 through the data signal line DW. The data strobe signals DQS output from the plurality of SDRAM are input to the data reception circuit 113 through the strobe signal line SW. The reception data signal RD is output from the data reception circuit 113, and input to the memory controller 104.
An input terminal of the data reception circuit 113 is provided with a terminating resistor (not shown) whose ON/OFF may be controlled. The terminating resistor is used to reduce reflection of an input signal, thereby enhancing waveform quality. The terminating resistor is required to be set to an ON-state during a read period for which data are input from the memory device 103 to the data reception circuit 113.
Furthermore, JP-A-2000-195263, JP-A-2007-115366 and JP-A-10-336008 disclose examples of other memory systems.
The time period from the output time of the read command from the memory controller device 102 to the input time of the data signal DQ and the data strobe signal DQS to the data reception circuit 113 is a round trip time. The round trip time contains a propagation delay time of the clock CK. The clock supply route to the plurality of SDRAMs in the memory device 103 is constructed by the daisy chain, and thus the length of the clock supply route is different for every SDRAM. Accordingly, a time lag occurs in the round trip time among the SDRAMs. To prevent signal line conflict, the period for which the terminating resistor is set to the ON-state is set to a period having a sufficiently larger margin than the actual read period. Accordingly, the occupation time of the signal line is lengthened, causing a drop in bus efficiency.